Discovering Cache Partitioning Optimizations for the K Computer

The processor architecture available on the K computer (SPARC64 VIIIfx) features an hardware cache partitioning mechanism called sector cache. This facility enables software to split the memory cache in two independent sectors: data loads in one sector cannot trigger the eviction of data in the second one. Moreover, software is responsible for data placement in each sector by issuing special instructions tagging the various memory loads performed during execution. The implementation details of this cache partitioning mechanism also enable fast redistribution of the cache during an application’s runtime, without any cost, allowing any optimization using the sector cache to be applied multiple times, with different setups, in the event of phase changes. Unfortunately, in its current state, the compilers provided on the K Computer do not implement any automatic optimization using this cache facility. In the contrary, the only high-level interface to this mechanism is a set of directive to instruct the compiler to generate tagging instructions over a code region. Thus, only application programmers with intricate knowledge of both the memory access patterns of their code and the K Computer architecture can take advantage of this facility. To address this issue and to study new optimization schemes using cache partitioning, we present in this paper a framework using binary instrumentation and reuse distance analysis to discover the locality of important data structures in an application and to suggest appropriate data distribution schemes for the sector cache. These optimizations are then translated into calls to the source-level API provided by the K Computer compilers. We applied our framework to analyze and optimize a set of HPC benchmarking applications and demonstrate significant performance improvements.